IC packaging solutions of all
A, IC encapsulation process
IC packaging history began in the mid - 1960 - s, fairchild company developed plastic dual-in-line package (PDIP), there are eight fuses. With the development of silicon technology, chip size is getting more and more big, accordingly cover will become bigger. To 60 s, has larger packaging lead appeared. At that time, people still don't pay attention to the appearance of compression device size, so the seal of the larger shell is also acceptable. But big cover take PCB area, and developed the ceramic chip carrier lead (LCCC). Asked in 1976 ~ 1977, its variants that plastic leaded carrier (PLCC), and live for about 10 years, the pin number has 16 ~ 132.
In the mid - 1980 - s developed four square flat pack (QFP) to replace the PLCC. At that time, a flange QFP (BQFP) and metric MQFP (MQFP) two kinds. But soon MQFP with its obvious advantages of replaced BQFP. Then there appeared a variety of modified, such as thin QFP (TQFP), fine pin spacing QFP (VQFP), narrow QFP (SQFP), plastic QFP (PQFP), metal QFP (MetalQFP), loading QFP (TapeQFP), etc. These QFP were suitable for SMT. But this kind of structure still takes too much PCB area, don't adapt to the requirement of further miniaturization. As a result, people begin to pay attention to reduce chip size, corresponding encapsulation also want as far as possible small. In fact, from 1968 to 1969, philips has developed a small outline package (SOP). Later gradually derived type J pin small package (SOJ), thin shape (TSOP), little appearance packaging (VSOP), narrow SOP (SSOP), thin, narrow SOP (TSSOP) and small transistor (SOT) shape, appearance IC (SOIC), etc. So, IC encapsulation shell has two broad categories: square flat and small shell. Circuit, the former is applicable to many pin circuit which is suitable for the little pin.
With the rapid development of semiconductor industry, the function of the chip more and more strong, the number of irfpa foot also need to continue to increase, then stay in surrounding the lead of the old mode, even if the interval then narrow the lead, its limitations are also increasingly prominent, and there a new concept of planar array, and the birth of array type packaging.
Array encapsulated pin grid array (PGA), was the first pin for pin type. Pin shape shifting into spherical convex point, namely the ball grid array (BGA); The ball to the pillar is column grid array (CGA). Then more loading BGA encapsulation (TBGA), metal BGA (MBGA), ceramic BGA (CBGA), the flipchip bonded BGA (FCBGA), plastic BGA (PBGA), enhanced encapsulation BGA (EPBGA), BGA chip size (D2BGA), small BOA (MiniBGA), microminiature BGA (MicroBGA) and the BGA (C2BGA) controlled collapse, etc. BGA become today's most active form of encapsulation.
Throughout history, people have tried not to give any IC encapsulation. One of the earliest developed in the 1960 s have IBM C4 (chip controlled collapse connection) technology. Later have a chip on board (COB), flexible chip on board (COF package) and chip (LOC) lead, etc. But the bare chip facing a confirm high quality chip (KGD is) problem. Both for IC and encapsulation are presented, and how much more the idea of "area", in 1992, Japan's Fujitsu, first proposed the concept of chip size package (CSP). International attention, soon it will become an important focus in the IC packaging.
Another form of encapsulation is about put forward in 1962, bell LABS by IBM in practice of carrier tape packaging (TCP). It was based on the flexible belt instead of the rigid plate as a carrier of a kind of encapsulation. Because of its expensive, processing time, has not been widely used.
The wide variety of packaging, in fact, from the 1960 s was born of encapsulation. Factors has been to promote the development of its power, weight, pin number, size, density, electrical characteristics, reliability, heat dissipation, price, etc.
Despite so many package to choose from, but the new packaging will also appear constantly. On the other hand, there are a lot of packaging designers and engineers are trying to get rid of encapsulation. , of course, it is never easy, encapsulation will also have to keep us company for 20 years, at least until the real chip only on a interconnection layer integration.
It can be roughly summed up the development of the encapsulation process: structure TO, DIP, LCC, QFP, BGA, CSP. Material is a ceramic metal plastic; Pin shape is short lead into a long wire or leadless pasted on a spherical convex point; Assembly is hole assembly installed on the surface of a directly.
Second, the IC encapsulation daqo
1, BGA (ballgridarray)
The spherical contact display, SMT type one of encapsulation. In the printing substrate on the back of the display mode to produce spherical convex point to replace pin, in the front of the printing substrate assembly LSI chips, then by moulding resin or potting method for sealing. Also known as the convex point display carrier (PAC). Pin can be more than 200, is one of the LSI with more pin encapsulation.
Encapsulation body also can do better than QFP (four side pin flat pack). Pin, for example, center distance of 1.5 mm 360 pin BGA is only 31 mm square; And pin center distance of 0.5 mm 304 pin QFP is 40 mm square. And BGA don't have to worry about QFP pin deformation problem.
The package was developed by Motorola companies in the United States, first of all be used in devices such as portable phone, in the future in the United States is likely to spread in the personal computer. Initially, BGA pin (convex point) of the center distance of 1.5 mm, pin number is 225. Now there are some manufacturer of LSI is developing 500 pin BGA. BGA problem after reflow soldering appearance inspection. It is unclear whether the appearance of the effective inspection method. Some think that due to large welding of center distance, connection can be regarded as a stable, only through a function to deal with.
Motorola companies in the United States call with sealed moulded resin encapsulation OMPAC, and called the potting method sealed packaging GPAC (see OMPAC and GPAC).
2, BQFP (quadflatpackagewithbumper)
With the four side of the pin cushion flat pack. One of QFP encapsulation, set in the four corners of the encapsulated ontology protrusions (cushion) in order to prevent the bending deformation occurred in the process of transporting pin. The semiconductor manufacturer mainly in microprocessor and ASIC circuit adopts the encapsulation. Pin center distance of 0.635 mm, pin number from 84 to 196 (see QFP).
3, touch welding PGA (buttjointpingridarray)
SMT type of PGA nickname (see surface-mount PGA).
4, C - (ceramic)
Mark said ceramic package. For example, CDIP represents ceramic DIP. In practice, however, is often used.
5, Cerdip
With glass sealed ceramic dual-in-line package, used for ECLRAM, DSP (digital signal processor), and other circuit. With a glass window Cerdip type used for ultraviolet erasing an EPROM and internal microcomputer with EPROM circuit, etc. Pin center distance of 2.54 mm, pin number from 8 to 42. In Japan, the packaging is expressed as DIP - G glass seal (G).
6, Cerquad
SMT type package, one of which is under the seal of the ceramic QFP, encapsulates DSP logic LSI circuit, etc. With a window Cerquad encapsulates an EPROM circuit. Good heat resistance than plastic QFP, under the condition of natural air cooling can allow 1.5 ~ 2 w power. But the packaging cost is higher than plastic QFP 3 ~ 5 times. Pin center distance is 1.27 mm, 0.8 mm and 0.65 mm, 0.5 mm and 0.4 mm, and other specifications. Pin number from 32 to 368.
7, CLCC (ceramicleadedchipcarrier)
With pin ceramic chip carrier, SMT type packaging, one of the pins from the encapsulation of four sides, a crowd.
With a window is used to encapsulate ultraviolet erasing an EPROM and microcomputer with EPROM circuit etc. The packaging is also known as QFJ, QFJ - G (see QFJ).
8, COB (chiponboard)
Board chip packaging, is one of the bare chip SMT technology, on printed circuit boards, semiconductor chips handover pasted on the chip and the electrical connection in the substrate with suture method, lead the electrical connection in the chip and the substrate with suture method, lead and resin covered in order to ensure reliability. Although the COB is the simplest bare chip SMT technology, but it is much less than the TAB and the packing density slice of welding technology.
9, the DFP (dualflatpackage)
Bilateral foot flat pack. Is the SOP nickname (see the SOP). Once there is the France has now basically don't have to.
10, DIC (dualin - lineceramicpackage)
Ceramic DIP (including glass seal) nickname (DIP).
11, DIL (dualin - line)
DIP the nickname (DIP). European semiconductor manufacturers use this name.
12, DIP (dualin - linepackage)
Dual-in-line package. Cartridge type packaging, one of the pins from the wrap on both sides of, packaging material, which has two kinds of plastic and ceramic. DIP is the most popular type instrumentation encapsulation, applications include standard logic IC, memory LSI, microcomputer circuit, etc. Pin center distance of 2.54 mm, pin number from 6 to 64. Encapsulation width usually is 15.2 mm. Some encapsulate width 7.52 mm and 7.52 mm respectively called skinnyDIP and slimDIP narrow size (DIP). But in most cases is not distinction, simply referred to as a DIP. In addition, with low melting point glass sealed ceramic DIP also called cerdip (see cerdip).
13, DSO (dualsmallout - lint)
Bilateral pin small outline package. SOP's nickname (see the SOP). Part of the semiconductor manufacturer use this name.
14, DICP (dualtapecarrierpackage)
Bilateral pin load encapsulation. One of the TCP (with packaging). Pin production carried and from the wrap on both sides of the insulation. Due to the use of "TAB (with automatic welding) technique, encapsulation shape is very thin. Often used for liquid crystal display driver LSI, but mostly on products. In addition, 0.5 mm thick shape memory LSI book packaging are under development. In Japan, according to the EIAJ electronic machinery industry (Japan) standards, named DICP DTP.
15, DIP (dualtapecarrierpackage)
Same as above. Japan will electronic machinery industry standard of DTCP naming (see DTCP).
16, FP (flatpackage)
Flat pack. One of the SMT type packaging. QFP or SOP (see) QFP and SOP's nickname. Part of the semiconductor manufacturer use this name.
17, flip chip
Chip welding. One of bare chip packaging technology, the LSI chip electrode area is made of metal protruding points, and then the metal protruding point with the printing substrate electrode area of pressure welding connection. Encapsulates the occupied area is basically the same as the chip size. Is that all the packaging technology in one of the smallest, the thinnest. But if the thermal expansion coefficient of substrate and LSI chip is different, will react in the joint, which affect the reliability of the connection. So must reinforce the LSI chips, with resin to thermal expansion coefficient and using essentially the same substrate material.
18, FQFP (finepitchquadflatpackage)
Traditional operas of QFP foot center. Usually guide foot center distance is less than 0.65 mm of QFP (see QFP). Part of the guide conductor manufacturers use this name.
19, the CPAC (globetoppadarraycarrier)
Motorola companies in the United States of BGA nickname (BGA).
20, CQFP (quadfiatpackagewithguardring)
The four side of the belt protection ring pin flat pack. Plastic one of QFP, pin protection ring masking with resin, in order to prevent the bending deformation.
Assemble at the LSI before printing substrate, cut off from the guard ring pin and make it become a sea gull wing shape (L). The encapsulation of Motorola company in the United States has batch production. Pin center distance of 0.5 mm, what is the maximum number of pins in around 208.
21, H - (withheatsink)
Said mark with the radiator. For example, HSOP means with the SOP of radiator.
22, pingridarray (surfacemounttype)
SMT type PGA. Usually PGA for instrumentation encapsulation, pin is about 3.4 mm long. Surface-mount PGA in encapsulation type bottom has display of the pins, the length from 1.5 mm to 2.0 mm. SMT printing substrate is used to touch welding method, therefore, also known as touch welding PGA. Because the pin center distance is only 1.27 mm, is smaller than cartridge type PGA half, not very big, so encapsulation ontology can be crafted and pin number is more than the cartridge type (250 ~ 528), is for the use of large scale logic LSI encapsulation. Encapsulation of the substrate has a multilayer ceramic substrate epoxy resin and glass printing base. With multilayer ceramic substrate encapsulation has practical application.
23, JLCC (J - leadedchipcarrier)
J shaped pin chip carrier. Refers to the window with CLCC and ceramic QFJ nickname with window (see CLCC and QFJ). Some manufacturers use the name of the semiconductor.
24, LCC (Leadlesschipcarrier)
No pin chip carrier. Refers to the four sides of the ceramic substrate electrode contact without pin but SMT type encapsulation. Is high speed and high frequency IC encapsulation, also known as ceramic QFN or QFN - C (see QFN).
25, the LGA (landgridarray)
Contact display packaging. Array in the bottom is what is state of the electrode contact encapsulation. Plug the socket assembly. Already practical have 227 contact center distance (1.27 mm) and 447 contact center distance (2.54 mm) of the LGA ceramic, applied to high-speed LSI logic circuit. The LGA compared with QFP, to accommodate with smaller package more input/output pin. In addition, because of the small lead impedance, is very suitable for high speed LSI. But because the socket production complex, high cost, now basically is not how to use. Is expected in the future the demand will increase.
26, LOC (leadonchip)
Chip fuses encapsulation. LSI packaging technology, one of the front end of the lead frame in a structure above the chip, chip near the center of the convex solder joints, sewn up with lead to electrical connections. And used to decorate the lead frame in the chip, compared to the structure of the near side of the same size in encapsulation hold about chip up to 1 mm in width.
27, LQFP (lowprofilequadflatpackage)
QFP thin. Refers to encapsulate the ontology of QFP thickness of 1.4 mm, is Japan's electronic machinery industry will be formulated according to the new QFP specifications used the name of the shape.
28, L - QUAD
One of the ceramic QFP. Packaging substrates with aluminum nitride, the thermal conductivity 7 ~ 8 times higher than the alumina and has good heat resistance. Encapsulated in the framework of alumina, chip seal with potting method, thus inhibiting the costs. Is a kind of packaging for the logic of the development of LSI, under the condition of natural air cooling can allow the power of the W3. Has developed 208 pin center distance (0.5 mm) and 160 pin center distance (0.65 mm) of LSI logic with encapsulation, and put into mass production in October 1993.
29, MCM (multi - chipmodule)
Chip components. Semiconductor bare chip assembly blocks on a wiring substrate of a kind of encapsulation. According to the substrate material can be divided into MCM -l, MCM - C and MCM -d three categories.
MCM - L is used usually multilayer printed substrate glass epoxy resin components. Wiring density is not very high, the cost is low.
MCM - C is the formation of multilayer wiring, with thick film technology in ceramic (alumina ceramic or glass) as the base plate component, and the use of multilayer ceramic substrate thick film hybrid IC similar. There was no significant difference. Wiring density higher than that of MCM - L.
MCM -d is form multilayer wiring with membrane technology, ceramic (alumina and aluminum nitride) or Si, Al component as the base plate. Wiring plot is the highest in the three components, but the cost is high.